The Confinity Low Latency Messaging (CLLM) software has recently undergone a significant transformation to harness the benefits of FPGA technology. In the new version, core functions and features are offloaded to the FPGA chip on the Alveo U50 card. This strategic move not only boosts the computing power of CLLM but also reduces OS platform dependencies and mitigates certain deficiencies. With nearly 1 million Look-Up Tables (LUTs), the Alveo U50 can handle both CLLM’s program logic and application-specific tasks effectively.

CLLM has been redeveloped and ported into a series of free-running kernels on the Alveo U50. These specialized kernels, tailored for TCP and UDP processing, efficiently handle CLLM messages at Ethernet line rates (in clock cycles).

The hardware-accelerated CLLM takes advantage of Xilinx’ Memory Mapped Slave Bridge shell and U50’s low latency network capability through 100G networking. It supports configurations like 4x 10GbE, 4x 25GbE, 1x 40GbE, or 1x 100GbE. Additionally, the FPGA’s excellent deep pipelining capability ensures minimal latency and maximized throughput.

Built with cutting-edge technology, CLLM on the Alveo U50 Data Center Accelerator Card delivers reliable, low-latency multicast messaging that is even more predictable, deterministic, and platform-agnostic.